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FEATURES Digitally Programmable Binary Gains from 1 to 16 Two-Chip Cascade Mode Achieves Binary Gain from 1 to 256 Gain Error: 0.01% Max, Gain = 1, 2, 4 (C Grade) 0.02% Max, Gain = 8, 16 (C Grade) 0.5 ppm/ C Drift Over Temperature Fast Settling Time 10 V Signal Change: 0.01% in 4.5 s (Gain = 16) Gain Change: 0.01% in 5.6 s (Gain = 16) Low Nonlinearity: 0.005% FSR Max (J Grade) Excellent DC Accuracy: Offset Voltage: 0.5 mV Max (C Grade) Offset Voltage Drift: 3 V/ C (C Grade) TTL-Compatible Digital Inputs PRODUCT DESCRIPTION
Software Programmable Gain Amplifier AD526
PIN CONFIGURATION
DIG GND 1 NULL 2 VIN 3 NULL 4
16 15 14
A1 A0 CS
CLK TOP VIEW ANALOG GND 2 5 (Not to Scale) 12 A2
AD526
13
ANALOG GND 1 6 -VS 7 VOUT SENSE 8
11 10 9
B +VS VOUT FORCE
The AD526 is a single-ended, monolithic software programmable gain amplifier (SPGA) that provides gains of 1, 2, 4, 8 and 16. It is complete, including amplifier, resistor network and TTL-compatible latched inputs, and requires no external components. Low gain error and low nonlinearity make the AD526 ideal for precision instrumentation applications requiring programmable gain. The small signal bandwidth is 350 kHz at a gain of 16. In addition, the AD526 provides excellent dc precision. The FETinput stage results in a low bias current of 50 pA. A guaranteed maximum input offset voltage of 0.5 mV max (C grade) and low gain error (0.01%, G = 1, 2, 4, C grade) are accomplished using Analog Devices' laser trimming technology. To provide flexibility to the system designer, the AD526 can be operated in either latched or transparent mode. The force/sense configuration preserves accuracy when the output is connected to remote or low impedance loads. The AD526 is offered in one commercial (0C to +70C) grade, J, and three industrial grades, A, B and C, which are specified from -40C to +85C. The S grade is specified from -55C to +125C. The military version is available processed to MILSTD 883B, Rev C. The J grade is supplied in a 16-lead plastic DIP, and the other grades are offered in a 16-lead hermetic side-brazed ceramic DIP.
APPLICATION HIGHLIGHTS
1. Dynamic Range Extension for ADC Systems: A single AD526 in conjunction with a 12-bit ADC can provide 96 dB of dynamic range for ADC systems. 2. Gain Ranging Preamps: The AD526 offers complete digital gain control with precise gains in binary steps from 1 to 16. Additional gains of 32, 64, 128 and 256 are possible by cascading two AD526s.
ORDERING GUIDE
Model AD526JN AD526AD AD526BD AD526CD AD526SD AD526SD/883B 5962-9089401MEA* Temperature Range Commercial Industrial Industrial Industrial Military Military Military Package Descriptions 16-Lead Plastic DIP 16-Lead Cerdip 16-Lead Cerdip 16-Lead Cerdip 16-Lead Cerdip 16-Lead Cerdip 16-Lead Cerdip Package Options N-16 D-16 D-16 D-16 D-16 D-16 D-16
*Refer to official DESC drawing for tested specifications.
REV. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD526-SPECIFICATIONS (@ V =
S
15 V, RL = 2 k
Min
and TA = +25 C unless otherwise noted)
Min AD526B/S Typ Max Min AD526C Typ Max Units
Model GAIN Gain Range (Digitally Programmable) Gain Error Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain Error Drift Over Temperature G=1 G=2 G=4 G=8 G = 16 Gain Error (TMIN to TMAX) Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Nonlinearity Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Nonlinearity (TMIN to TMAX) Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 VOLTAGE OFFSET, ALL GAINS Input Offset Voltage Input Offset Voltage Drift Over Temperature Input Offset Voltage TMIN to TMAX Input Offset Voltage vs. Supply (VS 10%) INPUT BIAS CURRENT Over Input Voltage Range 10 V ANALOG INPUT CHARACTERISTICS Voltage Range (Linear Operation) Capacitance RATED OUTPUT Voltage Current (VOUT = 10 V) Short-Circuit Current DC Output Resistance Load Capacitance (For Stable Operation)
Min
AD526J Typ
Max
AD526A Typ Max
1, 2, 4, 8, 16 0.05 0.05 0.10 0.15 0.15
1, 2, 4, 8, 16 0.02 0.03 0.03 0.07 0.07
1, 2, 4, 8, 16 0.01 0.02 0.02 0.04 0.04
1, 2, 4, 8, 16 0.01 0.01 0.01 0.02 0.02 % % % % %
0.5 0.5 0.5 0.5 1.0
2.0 2.0 3.0 5.0 5.0 0.06 0.06 0.12 0.17 0.17 0.005 0.001 0.001 0.001 0.001 0.01 0.001 0.001 0.001 0.001
0.5 0.5 0.5 0.5 1.0
2.0 2.0 3.0 5.0 5.0 0.03 0.04 0.04 0.08 0.08 0.005 0.001 0.001 0.001 0.001 0.01 0.001 0.001 0.001 0.001
0.5 0.5 0.5 0.5 1.0
2.0 2.0 3.0 5.0 5.0 0.02 0.03 0.03 0.05 0.05 0.005 0.001 0.001 0.001 0.001 0.01 0.001 0.001 0.001 0.001
0.5 0.5 0.5 0.5 1.0
2.0 2.0 3.0 5.0 5.0 0.015 0.015 0.015 0.03 0.03 0.0035 0.001 0.001 0.001 0.001 0.007 0.001 0.001 0.001 0.001
ppm/C ppm/C ppm/C ppm/C ppm/C % % % % % % FSR % FSR % FSR % FSR % FSR % FSR % FSR % FSR % FSR % FSR mV V/C mV dB
0.4 5
1.5 20 2.0
0.25 3
0.7 10 1.0
0.25 3
0.5 10 0.8
0.25 3
0.5 10 0.8
80 50 150
80 50 150
84 50 150
90 50 150
pA
10
12 5 12 10 30 0.002 700
10
12 5 12 10 30 0.002 700
10
12 5 12 10 30 0.002 700
10
12 5 12 10 30 0.002 700
V pF V mA mA pF
10 15
10 5 15
10 5 15
10 5 15
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REV. D
AD526
Model NOISE, ALL GAINS Voltage Noise, RTI 0.1 Hz to 10 Hz Voltage Noise Density, RTI f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz DYNAMIC RESPONSE -3 dB Bandwidth (Small Signal) G=1 G=2 G=4 G=8 G = 16 Signal Settling Time to 0.01% (VOUT = 10 V) G=1 G=2 G=4 G=8 G = 16 Full Power Bandwidth G = 1, 2, 4 G = 8, 16 Slew Rate G = 1, 2, 4 G = 8, 16 DIGITAL INPUTS (TMIN to TMAX) Input Current (VH = 5 V) Logic "1" Logic "0" TIMING1 (VL = 0.2 V, VH = 3.7 V) A0, A1, A2 TC TS TH B TC TS TH TEMPERATURE RANGE Specified Performance Storage POWER SUPPLY Operating Range Positive Supply Current Negative Supply Current PACKAGE OPTIONS Plastic (N-16) Ceramic DIP (D-16)
NOTES
1
Min
AD526J Typ
Max
Min
AD526A Typ Max
Min
AD526B/S Typ Max
Min
AD526C Typ Max
Units
3 70 60 30 25
3 70 60 30 25
3 70 60 30 25
3 70 60 30 35
V p-p nVHz nVHz nVHz nVHz
4.0 2.0 1.5 0.65 0.35
4.0 2.0 1.5 0.65 0.35
4.0 2.0 1.5 0.65 0.35
4.0 2.0 1.5 0.65 0.35
MHz MHz MHz MHz MHz
2.1 2.5 2.7 3.6 4.1 0.10 0.35 4 18 6 24
4 5 5 7 7
2.1 2.5 2.7 3.6 4.1 0.10 0.35 4 18 6 24
4 5 5 7 7
2.1 2.5 2.7 3.6 4.1 0.10 0.35 4 18 6 24
4 5 5 7 7
2.1 2.5 2.7 3.6 4.1 0.10 0.35 4 18 6 24
4 5 5 7 7
s s s s s MHz MHz V/s V/s
60 2 0
100
140 6 0.8
60 2 0
100
140 6 0.8
60 2 0
100
140 6 0.8
60 2 0
100
140 6 0.8
A V V
50 30 30 50 40 10 0 -65 4.5 10 10 AD526JN +70 +125 16.5 14 13
50 30 30 50 40 10 -40 -65 4.5 10 10 +85 +150 16.5 14 13
50 30 30 50 40 10 -40/-55 -65 4.5 10 10
50 30 30 50 40 30 +85/+125 -40 +150 -65 16.5 14 13 4.5 10 10 +85 +150 16.5 14 13
ns ns ns ns ns ns C C V mA mA
AD526AD
AD526BD AD526SD AD526SD/883B
AD526CD
Refer to Figure 25 for definitions. FSR = Full Scale Range = 20 V. RTI = Referred to Input.
Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
REV. D
-3-
AD526-Typical Performance Characteristics
20
30
V
20
V
OUTPUT VOLTAGE SWING -
OUTPUT VOLTAGE SWING -
INPUT BIAS CURRENT - pA
15 +25 C RL = 2k 10
15 VIN = 0 10
20 @ VS = 15V
10
5
5
0
0
5 10 SUPPLY VOLTAGE -
15 V
20
0 100
0
1k LOAD RESISTANCE -
10k
0
5 10 SUPPLY VOLTAGE -
15 V
20
Figure 1. Output Voltage Swing vs. Supply Voltage, G = 16
Figure 2. Output Voltage Swing vs. Load Resistance
Figure 3. Input Bias Current vs. Supply Voltage
100nA
75
20 10
16 8
10nA
INPUT BIAS CURRENT - pA
INPUT BIAS CURRENT
VS = 50
15V
4
GAIN
1nA
2 1 1
100pA
25
10pA
1pA -60
-20
20 60 100 TEMPERATURE - C
140
0 -10
-5 0 5 INPUT VOLTAGE - V
10
10
100
1k 10k 100k FREQUENCY - Hz
1M
10M
Figure 4. Input Bias Current vs. Temperature
Figure 5. Input Bias Current vs. Input Voltage
Figure 6. Gain vs. Frequency
25
FULL POWER RESPONSE - V p-p POWER SUPPLY REJECTION - dB
100
1.0002
15V WITH 1V p-p SINE WAVE
20
GAIN = 8, 16
80 +SUPPLY 60
15
GAIN = 1, 2, 4
NORMALIZED GAIN
1.0001
1.0000
10
40 -SUPPLY 20
0.9999
5
0 1k
10
10k
100k 1M FREQUENCY - Hz
10M
1
10
100 1k 10k FREQUENCY - Hz
100k
1M
0.9998 -60
-20
20 60 100 TEMPERATURE - C
140
Figure 7. Large Signal Frequency Response
Figure 8. PSRR vs. Frequency
Figure 9. Normalized Gain vs. Temperature, Gain = 1
-4-
REV. D
AD526
1000
INPUT NOISE VOLTAGE - nV/ Hz
0.006
0.004
NONLINEARITY - %FSR
0.002
100
0.000
-0.002
10 10
1k 100 10k FREQUENCY - Hz
100k
-0.004 -60
-20
20 60 100 TEMPERATURE - C
140
Figure 10. Noise Spectral Density
Figure 11. Nonlinearity vs. Temperature, Gain = 1
Figure 12. Wideband Output Noise, G = 16 (Amplified by 10)
Figure 13. Large Signal Pulse Response and Settling Time,* G=1
Figure 14. Small Signal Pulse Response, G = 1
Figure 15. Large Signal Pulse Response and Settling Time,* G=2
Figure 16. Small Signal Pulse Response, G = 2
Figure 17. Large Signal Pulse Response and Settling Time,* G=4
Figure 18. Small Signal Pulse Response, G = 4
*For Settling Time Traces, 0.01% = 1/2 Vertical Division
REV. D
-5-
AD526
Figure 19. Large Signal Pulse Response and Settling Time,* G = 8
Figure 20. Small Signal Pulse Response, G = 8
Figure 21. Large Signal Pulse Response and Settling Time,* G = 16
-60
TOTAL HARMONIC DISTORTION - dB
10
-70
PHASE DISTORTION - Dedrees
5
-80
0
-90
-5
-100 10
100
1k 10k FREQUENCY - Hz
100k
-10 10
100
1k 10k FREQUENCY - Hz
100k
Figure 22. Small Signal Pulse Response, Gain = 16
Figure 23. Total Harmonic Distortion vs. Frequency Gain = 16
Figure 24. Phase Distortion vs. Frequency, Gain = 16
100
OUTPUT IMPEDANCE -
G = 4, 16 10 G=1
G = 2, 8
1 10k
100k 1M FREQUENCY - Hz
10M
Figure 25. Output Impedance vs. Frequency
Figure 26. Gain Change Settling Time,** Gain Change: 1 to 2
Figure 27. Gain Change Settling Time,** Gain Change 1 to 4
*For Settling Time Traces, 0.01% = 1/2 Vertical Division **Scope Traces are: Top: Output Transition; Middle: Output Settling; Bottom: Digital Input.
-6-
REV. D
AD526
Figure 28. Gain Change Settling Time,* Gain Change 1 to 8
Figure 29. Gain Change Settling Time,* Gain Change 1 to 16
+15V -15V 10 F 10 F + +
+15V -15V 10 F + 10 F + TEKTRONIX 7000 SERIES SCOPE 7A13 PREAMP 5MHz BW
AD526
G = 16 OP37 900 G = 10 + 10 F +5V SHIELD 100
Vo = 160
e p-p
NOTE: COAX CABLE 1 FT. OR LESS
Figure 30. Wideband Noise Test Circuit
+15V -15V 10 F 10 F + + DATA DYNAMICS 5109 (OR EQUIVALENT FLAT-TOP PULSE GENERATOR) +15V -15V 5k 10 F + 10 F + 1pF + AD711 - - AD3554 + 5k IN6263 RIN 50 5pF - AD3554 + 10 F + 10 F + 5k IN6263 10 F + 10 F + TSET = TMEAS2 - TX2 1.25k G 1 2 4 8 16 TX 1.2 1.2 1.2 1.4 1.8 s s s s s VERROR 5k 5 TEKTRONIX 7000 SERIES SCOPE 7A13 PREAMP 5MHz BW
AD526
2k POT. 1pF VERROR
G 1 2 4 8 16
RIN 5.6k 2.8k 1.4k 715 348
5.6k
-15V +15V
-15V +15V
Figure 31. Settling Time Test Circuit
*Scope Traces are: Top: Output Transition Middle: Output Settling Bottom: Digital Input
REV. D
-7-
AD526
THEORY OF OPERATION TRANSPARENT MODE OF OPERATION
The AD526 is a complete software programmable gain amplifier (SPGA) implemented monolithically with a drift-trimmed BiFET amplifier, a laser wafer trimmed resistor network, JFET analog switches and TTL compatible gain code latches. A particular gain is selected by applying the appropriate gain code (see Table I) to the control logic. The control logic turns on the JFET switch that connects the correct tap on the gain network to the inverting input of the amplifier; all unselected JFET gain switches are off (open). The "on" resistance of the gain switches causes negligible gain error since only the amplifier's input bias current, which is less than 150 pA, actually flows through these switches. The AD526 is capable of storing the gain code, (latched mode), B, A0, A1, A2, under the direction of control inputs CLK and CS. Alternatively, the AD526 can respond directly to gain code changes if the control inputs are tied low (transparent mode). For gains of 8 and 16, a fraction of the frequency compensation capacitance (C1 in Figure 32) is automatically switched out of the circuit. This increases the amplifier's bandwidth and improves its signal settling time and slew rate.
AMPLIFIER +VS C1 C2 OUT FORCE
In the transparent mode of operation, the AD526 will respond directly to level changes at the gain code inputs (A0, A1, A2) if B is tied high and both CS and CLK are allowed to float low. After the gain codes are changed, the AD526's output voltage typically requires 5.5 s to settle to within 0.01% of the final value. Figures 26 to 29 show the performance of the AD526 for positive gain code changes.
A2 A1 A0 +VS +5V 0.1 F OUT 9 FORCE
16 A1
15
14
13
12
11 B
10
A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 1
VOUT GAIN NETWORK -
AD526
1 2 3 4 5 6
+ 7 8 OUT SENSE 0.1 F -VS
VIN
VIN
Figure 33. Transparent Mode
LATCHED MODE OF OPERATION
N1
N2 -VS OUT SENSE
A0 A1 A2 B CLK CS L A T C H E S
C O N T R O L L O G I C
14k G=8 3.4k G=2 1k G = 16 1.7k RESISTOR NETWORK
The latched mode of operation is shown in Figure 34. When either CS or CLK go to a Logic "1," the gain code (A0, A1, A2, B) signals are latched into the registers and held until both CS and CLK return to "0." Unused CS or CLK inputs should be tied to ground . The CS and CLK inputs are functionally and electrically equivalent.
TIMING SIGNAL A2 A1 A0 +VS +5V 0.1 F OUT 9 FORCE
G=4 DIGITAL GND ANALOG GND2 1k 1.7k ANALOG GND1
16 A1 15 14 13 12 11 B 10 A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 1 VOUT GAIN NETWORK -
Figure 32. Simplified Schematic of the AD526
AD526
1 2 3 4 5 6
+ 7 8 OUT SENSE 0.1 F -VS
VIN
Figure 34. Latched Mode
-8-
REV. D
AD526
TIMING AND CONTROL Table I. Logic Input Truth Table DIGITAL FEEDTHROUGH
Gain Code A2 A1 A0 B X 0 0 0 0 1 X X 0 0 0 0 1 X 0 0 1 1 X X X 0 0 1 1 X X 0 1 0 1 X X X 0 1 0 1 X X 1 1 1 1 1 0 0 1 1 1 1 1
Control CLK (CS = 0) 1 0 0 0 0 0 0 1 1 1 1 1 1
Condition Gain Previous State 1 2 4 8 16 1 1 1 2 4 8 16
Condition Latched Transparent Transparent Transparent Transparent Transparent Transparent Latched Latched Latched Latched Latched Latched
With either CS or CLK or both held high, the AD526 gain state will remain constant regardless of the transitions at the A0, A1, A2 or B inputs. However, high speed logic transitions will unavoidably feed through to the analog circuitry within the AD526 causing spikes to occur at the signal output. This feedthrough effect can be completely eliminated by operating the AD526 in the transparent mode and latching the gain code in an external bank of latches (Figure 36). To operate the AD526 using serial inputs, the configuration shown in Figure 36 can be used with the 74LS174 replaced by a serial-in/parallel-out latch, such as the 54LS594.
A1 A0 A2 B +5V 1F TIMING SIGNAL 74LS174
+VS 0.1 F OUT 9 FORCE
NOTE: X = Don't Care.
The specifications on page 3, in combination with Figure 35, give the timing requirements for loading new gain codes.
16 A1 GAIN CODE INPUTS TC CLK OR CS TS TC = MINIMUM CLOCK CYCLE TS = DATA SETUP TIME TH = DATA HOLD TIME TH NOTE: THRESHOLD LEVEL FOR GAIN CODE, CS, AND CLK IS 1.4V. VIN -VS 1 GAIN NETWORK - VALID DATA 15 14 13 12 11 B 10 A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 1
VOUT
AD526
2 3 4 5 6
+ 7 8 OUT SENSE 0.1 F
Figure 35. AD526 Timing
Figure 36. Using an External Latch to Minimize Digital Feedthrough
REV. D
-9-
AD526
GROUNDING AND BYPASSING
Proper signal and grounding techniques must be applied in board layout so that specified performance levels of precision data acquisition components, such as the AD526, are not degraded. As is shown in Figure 37, logic and signal grounds should be separate. By connecting the signal source ground locally to the AD526 analog ground Pins 5 and 6, gain accuracy of the AD526 is maintained. This ground connection should not be corrupted by currents associated with other elements within the system.
+15V -15V 0.1 F 0.1 F
Utilizing the force and sense outputs of the AD526, as shown in Figure 38, avoids signal drops along etch runs to low impedance loads.
Table II. Logic Table for Figure 38
VOUT/VIN 1 2 4 8 16 32 64 128
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
VIN 0.1 F ANALOG ANALOG +VS GROUND 1 GROUND 2 AMP GAIN NETWORK LATCHES AND LOGIC VOUT SENSE DIGITAL GROUND 0.1 F -VS VOUT FORCE
AD574 12-BIT A/D CONVERTER
AD526
1F +5V
Figure 37. Grounding and Bypassing
CLK A2 A1 A0 +VS +5V 0.1 F OUT 9 FORCE +5V +VS 0.1 F OUT 9 FORCE
16 A1
15
14
13
12
11 B
10
16 A1
15
14
13
12
11 B
10
A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 1
A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 1
VOUT GAIN NETWORK - GAIN NETWORK - + 3 4 5 6 7 8 OUT SENSE 1
AD526
1 2
AD526
2 3 4 5 6
+ 7 8 OUT SENSE 0.1 F
VIN
0.1 F -VS -VS
Figure 38. Cascaded Operation
-10-
REV. D
AD526
OFFSET NULLING CASCADED OPERATION
Input voltage offset nulling of the AD526 is best accomplished at a gain of 16, since the referred-to-input (RTI) offset is amplified the most at this gain and therefore is most easily trimmed. The resulting trimmed value of RTI voltage offset typically varies less than 3 V across all gain ranges. Note that the low input current of the AD526 minimizes RTI voltage offsets due to source resistance.
+VS 0.1 F OUT 9 FORCE
A cascade of two AD526s can be used to achieve binarily weighted gains from 1 to 256. If gains from 1 to 128 are needed, no additional components are required. This is accomplished by using the B pin as shown in Figure 38. When the B pin is low, the AD526 is held in a unity gain stage independent of the other gain code values.
OFFSET NULLING WITH A D/A CONVERTER
16 A1
15
14
13
12
11 B
10
A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 1
VOUT GAIN NETWORK -
AD526
1 VIN 20k 2 3 4 5 6
+ 7 8 OUT SENSE 0.1 F -VS
Figure 41 shows the AD526 with offset nulling accomplished with an 8-bit D/A converter (AD7524) circuit instead of the potentiometer shown in Figure 39. The calibration procedure is the same as before except that instead of adjusting the potentiometer, the D/A converter corrects for the offset error. This calibration circuit has a number of benefits in addition to eliminating the trimpot. The most significant benefit is that calibration can be under the control of a microprocessor and therefore can be implemented as part of an autocalibration scheme. Secondly, dip switches or RAM can be used to hold the 8-bit word after its value has been determined. In Figure 42 the offset null sensitivity, at a gain of 16, is 80 V per LSB of adjustment, which guarantees dc accuracy to the 16-bit performance level.
+VS 0.1 F OUT 9 FORCE
Figure 39. Offset Voltage Null Circuit
16 15 14 13 12 11 B 10
OUTPUT CURRENT BOOSTER
A1
The AD526 is rated for a full 10 V output voltage swing into 2 k. In some applications, the need exists to drive more current into heavier loads. As shown in Figure 40, a high current booster may be connected "inside the loop" of the SPGA to provide the required current boost without significantly degrading overall performance. Nonlinearities, offset and gain inaccuracies of the buffer are minimized by the loop gain of the AD526 output amplifier.
+VS 0.1 F
MSB
A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 1
VOUT
GAIN NETWORK
-
AD526
1 VIN
AD581 OR AD587 +10V VREF
+ 3 4 5 6 7 8 OUT SENSE 0.1 F
2
+VS
3.3M
7.5M
-VS
ALL BYPASS CAPACITORS ARE 0.1 F
+VS
1k OUT 1 OUT 2 10 F
0.01 F - AD548 + 0.01 F
16 A1
15
14
13
12
11 B
10
OUT 9 FORCE
LSB
0.01 F
CS WR
AD7524
A0 CS CLK A2 LOGIC AND LATCHES 16 8 4 2 1
HOS-100
GND
-VS
GAIN NETWORK - 0.01 F
Figure 41. Offset Nulling Using a DAC
AD526
1 2 3 4 5 6
+ 7 8 OUT SENSE
VIN
0.1 F RL -VS
Figure 40. Current Output Boosting
REV. D
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AD526
FLOATING-POINT CONVERSION
High resolution converters are used in systems to obtain high accuracy, improve system resolution or increase dynamic range. There are a number of high resolution converters available with throughput rates of 66.6 kHz that can be purchased as a single component solution; however in order to achieve higher throughput rates, alternative conversion techniques must be employed. A floating point A/D converter can improve both throughput rate and dynamic range of a system. In a floating point A/D converter (Figure 42), the output data is presented as a 16-bit word, the lower 12 bits from the A/D converter form the mantissa and the upper 4 bits from the digital signal used to set the gain form the exponent. The AD526 programmable gain amplifier in conjunction with the comparator circuit scales the input signal to a range between half scale and full scale for the maximum usable resolution. The A/D converter diagrammed in Figure 42 consists of a pair of AD585 sample/hold amplifiers, a flash converter, a five-range programmable gain amplifier (the AD526) and a fast 12-bit A/D converter (the AD7572). The floating-point A/D converter achieves its high throughput rate of 125 kHz by overlapping the acquisition time of the first sample/hold amplifier and the settling time of the AD526 with the conversion time of the A/D converter. The first sample/hold amplifier holds the signal for the flash autoranger, which determines which binary quantum
the input falls within, relative to full scale. Once the AD526 has settled to the appropriate level, then the second sample/hold amplifier can be put into hold which holds the amplified signal while the AD7572 perform its conversion routine. The acquisition time for the AD585 is 3 s, and the conversion time for the AD7572 is 5 s for a total of 8 s, or 125 kHz. This performance relies on the fast settling characteristics of the AD526 after the flash autoranging (comparator) circuit quantizes the input signal. A 16-bit register holds the 3-bit output from the flash autoranger and the 12-bit output of the AD7572. The A/D converter in Figure 42 has a dynamic range of 96 dB. The dynamic range of a converter is the ratio of the full-scale input range to the LSB value. With a floating-point A/D converter the smallest value LSB corresponds to the LSB of the monolithic converter divided by the maximum gain of the PGA. The floating point A/D converter has a full-scale range of 5 V, a maximum gain of 16 V/V from the AD526 and a 12-bit A/D converter; this produces: LSB = ([FSR/2N]/Gain) = ([5 V/4096]/16) = 76 V. The dynamic range in dBs is based on the log of the ratio of the full-scale input range to the LSB; dynamic range = 20 log (5 V/76 V) = 96 dB.
-15V +15V +5V +5V 30pF 74123 1/2 1/6 4 50k 10 F +5V VIN 68pF 2.5MHz 68pF AD7572 -15V +15V + + 10 F 10 F + + 10 F 5 BUSY MSB D12 D11 1s -15V +15V -15V +15V 10 F + + 10 F F 10 F + + 10 F S/H AD585 74- LS174 D10 D9 D8 D7 1/6 6 +5V
CLOCK 125MHz
1
1/6
3 2
10k
AD526
VIN +5V VIN S/H AD585 B
S 47 F
D6 D5 LSB 74- LS174 D4 D3 D2 D1
A0 A1 A2
10k
-15V +15V 10 F + + AD588 2.5k 1F 10 F
+5V A0 10k +5VREF 10k 5k 10k 4 5 10k 9 10 1.25k 10k 11 1/6 10 1/4 8 1/4 6 NOTE: ALL BYPASS CAPACITORS ARE 0.1 F 74ALS86 1 3 2 1/4 A1 12 13 1/4 11 A2 74- LS174 E1 E2 E3
1 2
1/4
3
1.25k
LM339A
Figure 42. Floating-Point A/D Converter
-12-
REV. D
AD526
HIGH ACCURACY A/D CONVERTERS
Very high accuracy and high resolution floating-point A/D converters can be achieved by the incorporation of offset and gain calibration routines. There are two techniques commonly used for calibration, a hardware circuit as shown in Figure 43 and/or a software routine. In this application the microprocessor is functioning as the autoranging circuit, requiring software overhead; therefore, a hardware calibration technique was applied which reduces the software burden. The software is used to set the gain of the AD526. In operation the signal is converted, and if the MSB of the AD574 is not equal to a Logical 1, the gain is increased by binary steps, up to the maximum gain. This maximizes the full-scale range of the conversion process and insures a wide dynamic range. The calibration technique uses two point correction, offset and gain. The hardware is simplified by the use of programmable magnitude comparators, the 74ALS528s, which can be "burned" for a particular code. In order to prevent under or over range
hunting during the calibration process, the reference offset and gain codes should be different from the endpoint codes. A calibration cycle consists of selecting whether gain or offset is to be calibrated then selecting the appropriate multiplexer channel to apply the reference voltage to the signal channel. Once the operation has been initiated, the counter, a 74ALS869, drives the D/A converter in a linear fashion providing a small correction voltage to either the gain or offset trim point of the AD574. The output of the A/D converter is then compared to the value preset in the 74ALS528 to determine a match. Once a match is detected, the 74ALS528 produces a low going pulse which stops the counter. The code at the D/A converter is latched until the next calibration cycle. Calibration cycles are under the control of the microprocessor in this application and should be implemented only during periods of converter inactivity.
+5V 200pF 10 F +
+15V -15V 10 F +
-15V +15V NOISE REDUCTION 1F +15V R8 A1 R1 R2 R3 A2 R5 R6 AD588 R4 A4 +VS -VS 0.1 F 0.1 F -5V +15V SYS GND -15V A3 +5V AD7501 10k F S AD574 -15V +15V VREF WR 50k -15V DECODED WR ADDRESS DECODED ADDRESS DECODED ADD +5V OP27 1k AD585 2 7404 1
MSB
DATA BUS
VIN1 VIN2 VIN3 VIN4
AD526
LSB
WR
ADDRESS BUS 12 +5V CALIBRATION PRESET +5V VALUE R5 20k A2 GAIN AD712 12
MSB 74ALS 528 P=Q GAIN 7475 1/2 PIN 28 AD574
+5V 5k VREF
PIN 15 AD588
R62 20k R72 10k R11 5k A1 AD712
1 3 2 7400
MSB INPUT BUFFER
AD7628 LATCH
RFB A
R21 C12
DAC A
OUT A
AGND
ADG221 LSB MSB 74ALS 528 P=Q OFFSET +5V 7475 1/2 +5V 7475 4 6 5 7400 WR
74ALS 869
RFB B CONTROL LOGIC
R41 C22
LSB
LATCH
DAC B
OUT B
A3 R8 20k A2 OFFSET AD712
WR
A/B VREF
AD712 R92 AGND 10k R102 20k PIN 15 AD588 R12 5k
AGND NOTE: ALL BYPASS CAPACITORS ARE 0.1 F LSB
+5V
Figure 43. High Accuracy A/D Converter
REV. D
-13-
AD526
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic DIP Package (N-16)
0.87 (22.1) MAX
16 1 9 8
16-Lead Sided-Brazed Ceramic Package (D-16)
0.25 0.31 (6.25) (7.87) 0.035 (0.89) 0.18 (4.57) 0.3 (7.62) 0.18 (4.57) MAX 0.011 (0.28)
PIN 1
0.040R 16 0.310 0.01 (7.874 0.254)
9
0.265 0.290 0.010 (6.73) (7.37 0.254)
8
1
0.125 (3.18) MIN 0.018 (0.46) 0.100 (2.54) 0.033 (0.84)
PIN 1 0.800 (20.32
0.010 0.254) 0.035 0.01 (0.889 0.254)
SEATING PLANE
0.095 (2.41) 0.180 0.03 (4.57 0.762) 0.047 (1.19 0.007 0.18) 0.017 +0.003 -0.002 (0.43 +0.076 ) -0.05 0.700 (17.78) BSC
0.300 (7.62) REF 0.085 (2.159)
0.125 (3.175) MIN 0.100 (2.54) SEATING BSC PLANE 0.010 0.002 (0.254 0.05)
-14-
REV. D
PRINTED IN U.S.A.
C1103d-0-8/99
0.430 (10.922)

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